Evaluating the Impact of Designing and Testing of High Performance Pipeline Functional Units by Using Verilog Hardware Description Language about Superscalar and DSP Processors and their Usage in Complex DSP Algorithms

Özet

In thisresearch, the researcher presented pipelining of functional units in superscalar and DSP Processors, using Verilog hardware description language (VHDL). The purpose of this Research was to increase the efficiency and computation performance of superscalar and DSP Processors making it cost effective due to the parallel execution of tasks. Previously work done regarding this has produced serial execution of instructions that used to take much more time in the execution of single instruction and after completion of that instruction, next instruction is to be executed, which simply produces time load in Superscalar and DSP processors. To resolve this matter much hardware (registers, adders, Multiplexers, decoder, encoders) was used. Although it improved computing performance yet it became costly and became out of range of pocket. Through this research, the researcher aimed to produce such an architecture that not only increases computation performance but also is cost effective as well. Parallel processing has been introduced through which we break the process into a series of steps. Each step transforms the previous step through refinement. The investigation was concluded with a summary of the researcher's conclusions, comments, and recommendations.